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ISCA
2012
IEEE
279views Hardware» more  ISCA 2012»
11 years 10 months ago
Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
Rachata Ausavarungnirun, Kevin Kai-Wei Chang, Lava...
VRCAI
2004
ACM
14 years 27 days ago
Explorative construction of virtual worlds: an interactive kernel approach
Despite steady research advances in many aspects of virtual reality, building and testing virtual worlds remains to be a very difficult process. Most virtual environments are stil...
Jinseok Seo, Gerard Jounghyun Kim
SC
2009
ACM
14 years 2 months ago
Scalable temporal order analysis for large scale debugging
We present a scalable temporal order analysis technique that supports debugging of large scale applications by classifying MPI tasks based on their logical program execution order...
Dong H. Ahn, Bronis R. de Supinski, Ignacio Laguna...
NETWORK
2008
96views more  NETWORK 2008»
13 years 7 months ago
Enabling rapid wireless system composition through layer-2 discovery
Although small mobile computers have processors whose capabilities are increasing, often they still are resource constrained in terms of performing many common computing tasks. Co...
Shivani Sud, Roy Want, Trevor Pering, Barbara Rosa...
CASES
2004
ACM
14 years 28 days ago
Balancing design options with Sherpa
Application specific processors offer the potential of rapidly designed logic specifically constructed to meet the performance and area demands of the task at hand. Recently, t...
Timothy Sherwood, Mark Oskin, Brad Calder