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» The scaling of interconnect buffer needs
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CNSR
2010
IEEE
164views Communications» more  CNSR 2010»
13 years 11 months ago
Buffered Crossbar Fabrics Based on Networks on Chip
— Buffered crossbar (CICQ) switches have shown a high potential in scaling Internet routers capacity. However, they require expensive on-chip buffers whose cost grows quadratical...
Lotfi Mhamdi, Kees Goossens, Iria Varela Senin
ASPDAC
2005
ACM
100views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Microarchitecture evaluation with floorplanning and interconnect pipelining
— As microprocessor technology continues to scale into the nanometer regime, recent studies show that interconnect delay will be a limiting factor for performance, and multiple c...
Ashok Jagannathan, Hannah Honghua Yang, Kris Konig...
NOCS
2010
IEEE
13 years 5 months ago
Design of a High-Throughput Distributed Shared-Buffer NoC Router
Router microarchitecture plays a central role in the performance of an on-chip network (NoC). Buffers are needed in routers to house incoming flits which cannot be immediately forw...
Rohit Sunkam Ramanujam, Vassos Soteriou, Bill Lin,...
ICCS
2007
Springer
14 years 1 months ago
Implementing Virtual Buffer for Electric Power Grids
The electric power grid is a vital network for every aspect of our life. The lack of buffer between generation and consumption makes the power grid unstable and fragile. While larg...
Rong Gao, Lefteri H. Tsoukalas
SIGCOMM
2012
ACM
11 years 10 months ago
On-chip networks from a networking perspective: congestion and scalability in many-core interconnects
In this paper, we present network-on-chip (NoC) design and contrast it to traditional network design, highlighting similarities and differences between the two. As an initial case...
George Nychis, Chris Fallin, Thomas Moscibroda, On...