86 search results - page 12 / 18 » The state of SAT |
GLVLSI
2009
IEEE
14 years 2 months ago
2009
IEEE
The sequential depth determines the completeness of bounded model checking in design verification. Recently, a SATbased method is proposed to compute the sequential depth of a de...
AB
2007
Springer
13 years 11 months ago
2007
Springer
Abstract. Haplotype inference from genotype data is a key computational problem in bioinformatics, since retrieving directly haplotype information from DNA samples is not feasible ...
FMCAD
2000
Springer
13 years 11 months ago
2000
Springer
Image computation nds wide application in VLSI CAD, such as state reachability analysis in formal veri cation and synthesis, combinational veri cation, combinational and sequential...
INDOCRYPT
2010
Springer
13 years 5 months ago
2010
Springer
Abstract. This paper presents the first results on AIDA/cube, algebraic and sidechannel attacks on variable number of rounds of all members of the KATAN family of block ciphers. Ou...
CAV
2012
Springer
11 years 10 months ago
2012
Springer
A SAT-based incremental, inductive algorithm for model checking CTL properties is proposed. As in classic CTL model checking, the parse graph of the property shapes the analysis. H...