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» The use of random simulation in formal verification
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ASPDAC
2006
ACM
141views Hardware» more  ASPDAC 2006»
13 years 11 months ago
Depth-driven verification of simultaneous interfaces
The verification of modern computing systems has grown to dominate the cost of system design, often with limited success as designs continue to be released with latent bugs. This t...
Ilya Wagner, Valeria Bertacco, Todd M. Austin
FMCAD
2006
Springer
13 years 11 months ago
Design for Verification of the PCI-X Bus
The importance of re-usable Intellectual Properties (IPs) cores is increasing due to the growing complexity of today's system-on-chip and the need for rapid prototyping. In th...
Haja Moinudeen, Ali Habibi, Sofiène Tahar
EUROCRYPT
2000
Springer
13 years 11 months ago
Provably Secure Password-Authenticated Key Exchange Using Diffie-Hellman
Abstract. When designing password-authenticated key exchange protocols (as opposed to key exchange protocols authenticated using cryptographically secure keys), one must not allow ...
Victor Boyko, Philip D. MacKenzie, Sarvar Patel
ECRTS
1998
IEEE
13 years 12 months ago
Tool-supported hierarchical design of distributed real-time systems
In this paper we demonstrate the usage of a formal description technique for real-time systems called PLCAutomaton [4] by applying this method to a real-world case study. To this ...
Henning Dierks, Josef Tapken
ICTAI
1997
IEEE
13 years 11 months ago
GA-Based Performance Analysis of Network Protocols
This paper tackles the problem of analyzing the correctness and performance of a computer network protocol. Given the complexity of the problem, no currently used technique is abl...
Mario Baldi, Fulvio Corno, Maurizio Rebaudengo, Gi...