145 search results - page 19 / 29 » The use of random simulation in formal verification |
EMSOFT
2008
Springer
13 years 9 months ago
2008
Springer
The Simulink/Stateflow (SL/SF) environment from Mathworks is becoming the de facto standard in industry for model based development of embedded control systems. Many commercial to...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
The challenge of verifying a modern microprocessor design is an overwhelming one: Increasingly complex micro-architectures combined with heavy time-to-market pressure have forced ...
DAC
2010
ACM
13 years 11 months ago
2010
ACM
Effective system verification requires good specifications. The lack of sufficient specifications can lead to misses of critical bugs, design re-spins, and time-to-market slips. I...
CODES
2008
IEEE
13 years 9 months ago
2008
IEEE
Functional validation is a major bottleneck in microprocessor design methodology. Simulation is the widely used method for functional validation using billions of random and biase...
FMCAD
2000
Springer
13 years 11 months ago
2000
Springer
BLIF is a hardware description language designed for the hierarchical description of sequential circuits. We give a denotational semantics for BLIF-MV, a popular dialect of BLIF, t...