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CASES
2003
ACM
14 years 3 months ago
Frequent loop detection using efficient non-intrusive on-chip hardware
Dynamic software optimization methods are becoming increasingly popular for improving software performance and power. The first step in dynamic optimization consists of detecting ...
Ann Gordon-Ross, Frank Vahid
LCTRTS
1999
Springer
14 years 2 months ago
Effective Exploitation of a Zero Overhead Loop Buffer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...
Gang-Ryung Uh, Yuhong Wang, David B. Whalley, Sanj...
WCET
2010
13 years 8 months ago
Towards WCET Analysis of Multicore Architectures Using UPPAAL
To take full advantage of the increasingly used shared-memory multicore architectures, software algorithms will need to be parallelized over multiple threads. This means that thre...
Andreas Gustavsson, Andreas Ermedahl, Björn L...
IPPS
2007
IEEE
14 years 5 months ago
Software and Algorithms for Graph Queries on Multithreaded Architectures
Search-based graph queries, such as finding short paths and isomorphic subgraphs, are dominated by memory latency. If input graphs can be partitioned appropriately, large cluster...
Jonathan W. Berry, Bruce Hendrickson, Simon Kahan,...
ASPLOS
2009
ACM
14 years 11 months ago
RapidMRC: approximating L2 miss rate curves on commodity systems for online optimizations
Miss rate curves (MRCs) are useful in a number of contexts. In our research, online L2 cache MRCs enable us to dynamically identify optimal cache sizes when cache-partitioning a s...
David K. Tam, Reza Azimi, Livio Soares, Michael St...