248 search results - page 10 / 50 » Threaded Multiple Path Execution |
ISCA
1994
IEEE
14 years 22 days ago
1994
IEEE
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...
ASPLOS
2006
ACM
14 years 10 days ago
2006
ACM
Transient faults are expected a be a major design consideration in future microprocessors. Recent proposals for transient fault detection in processor cores have revolved around t...
HOTSWUP
2009
ACM
13 years 6 months ago
2009
ACM
Dynamic software update is a technique by which a running program can be updated with new code and data without interrupting its execution. Often we will want to preserve properti...
RTSS
2006
IEEE
14 years 2 months ago
2006
IEEE
Modern FPGA devices, which include (multiple) processor core(s) as diffused IP on the silicon die, provide an excellent platform for developing custom multiprocessor systems-on-pr...
HIPEAC
2011
Springer
12 years 8 months ago
2011
Springer
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...