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FPL
2005
Springer
119views Hardware» more  FPL 2005»
14 years 2 months ago
Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes
This paper presents a revised model for the yield analysis of FPGA interconnect layers. Based on proven yield models, this work improves the predictions and assumptions of previous...
Nicola Campregher, Peter Y. K. Cheung, George A. C...
EURODAC
1995
IEEE
152views VHDL» more  EURODAC 1995»
14 years 17 days ago
Information model of a compound graph representation for system and architecture level design
In order to extract a suitable common core information model, design representations on both system and architecture levels are analyzed. Following the specification trajectory, ...
Peter Conradi
JAR
2008
124views more  JAR 2008»
13 years 9 months ago
Formal Verification of a C-like Memory Model and Its Uses for Verifying Program Transformations
This article presents the formal verification, using the Coq proof assistant, of a memory model for low-level imperative languages such as C and compiler intermediate languages. Be...
Xavier Leroy, Sandrine Blazy
CCE
2004
13 years 8 months ago
Nonequilibrium modeling of three-phase distillation
A nonequilibrium (NEQ) model for a complete three-phase distillation in tray columns is described. The model consists of a set of mass and energy balances for each of the three po...
A. Higler, R. Chande, R. Taylor, R. Baur, R. Krish...
ICPR
2006
IEEE
14 years 10 months ago
Initialization and System Modeling in 3-D Pose Tracking
Initialization and choice of adequate motion models are two important but seldom discussed problems in 3D modelbased pose (position and orientation) tracking. In this paper, we pr...
Danica Kragic, Ville Kyrki