Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes

This paper presents a revised model for the yield analysis of FPGA interconnect layers. Based on proven yield models, this work improves the predictions and assumptions of previously reported analysis. The model is then applied to three well known yield improvement schemes to quantify the enhancement offered by these schemes.

• Type: Conference
• Year: 2005
• Where: FPL
• Authors: Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko
• Keywords: FPL 2005, Proven Yield Models, Yield Analysis, Yield Improvement Schemes