Timing optimizations during logic synthesis has become a necessary step to achieve timing closure in VLSI designs. This often involves “shortening” all paths found in the circ...
Process improvement is a challenging task for software engineering. As Kuvaja [7]. has stated it:” It is difficult to find a unique way to identify a common improvement path suit...
By allowing end hosts to make independent routing decisions at the application level, different overlay networks may unintentionally interfere with each other. This paper describes...
—The performance of 802.11-based multi-channel wireless mesh networks is affected by the interference due to neighboring nodes operating on same or adjacent channels. In this pap...
Wee Lum Tan, Konstanty Bialkowski, Marius Portmann
We consider the problem of distributed channel estimation in a sensor network which employs a random sleep strategy to conserve energy. If the N network nodes are randomly placed a...