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135
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ATS
2005
IEEE
98views Hardware» more  ATS 2005»
15 years 9 months ago
Untestable Multi-Cycle Path Delay Faults in Industrial Designs
The need for high-performance pipelined architectures has resulted in the adoption of latch based designs with multiple, interacting clocks. For such designs, time sharing across ...
Manan Syal, Michael S. Hsiao, Suriyaprakash Natara...
111
Voted
NOSSDAV
2004
Springer
15 years 9 months ago
Passive inference of path correlation
Overlays have been proposed as a means to improve application performance in many areas, including multimedia streaming and content distribution. Some overlays use parallel transm...
Lili Wang, Jim Griffioen, Kenneth L. Calvert, Sher...
125
Voted
ICWL
2010
Springer
15 years 1 months ago
An Open Model for Learning Path Construction
Learning path construction is a complex task. It involves formulating and organizing learning activities, defining ways to evaluate student learning progress and to match such prog...
Fan Yang, Frederick W. B. Li, Rynson W. H. Lau
140
Voted
PAMI
2010
222views more  PAMI 2010»
15 years 2 months ago
Minimal Surfaces Extend Shortest Path Segmentation Methods to 3D
—Shortest paths have been used to segment object boundaries with both continuous and discrete image models. Although these techniques are well defined in 2D, the character of the...
Leo Grady
111
Voted
ASPLOS
2006
ACM
15 years 9 months ago
A spatial path scheduling algorithm for EDGE architectures
Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed mi...
Katherine E. Coons, Xia Chen, Doug Burger, Kathryn...