132 search results - page 13 / 27 » Three-Dimensional Cache Design Exploration Using 3DCacti |
TCAD
2002
13 years 7 months ago
2002
System-on-a-chip (SOC) platform manufacturers are increasingly adding configurable features that provide power and performance flexibility in order to increase a platform's ap...
CODES
2010
IEEE
13 years 5 months ago
2010
IEEE
Today, mobile smartphones are expected to be able to run the same complex, algorithm-heavy, memory-intensive applications that were originally designed and coded for generalpurpos...
VIS
2004
IEEE
14 years 8 months ago
2004
IEEE
Typically there is a high coherence in data values between neighboring time steps in an iterative scientific software simulation; this characteristic similarly contributes to a co...
IPCCC
2006
IEEE
14 years 1 months ago
2006
IEEE
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
JEC
2006
13 years 7 months ago
2006
This paper explores power consumption for destructive-read embedded DRAM. Destructive-read DRAM is based on conventional DRAM design, but with sense amplifiers optimized for lower ...