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ICCD
2004
IEEE
125views Hardware» more  ICCD 2004»
14 years 4 months ago
IPC Driven Dynamic Associative Cache Architecture for Low Energy
Existing schemes for cache energy optimization incorporate a limited degree of dynamic associativity: either direct mapped or full available associativity (say 4-way). In this pap...
Sriram Nadathur, Akhilesh Tyagi
IEEEPACT
2007
IEEE
14 years 1 months ago
Verification-Aware Microprocessor Design
The process of verifying a new microprocessor is a major problem for the computer industry. Currently, architects design processors to be fast, power-efficient, and reliable. Howe...
Anita Lungu, Daniel J. Sorin
CF
2005
ACM
13 years 9 months ago
A case for a working-set-based memory hierarchy
Modern microprocessor designs continue to obtain impressive performance gains through increasing clock rates and advances in the parallelism obtained via micro-architecture design...
Steve Carr, Soner Önder
VRST
2003
ACM
14 years 24 days ago
Tele-sports and tele-dance: full-body network interaction
Researchers have had great success using motion capture tools for controlling avatars in virtual worlds. Another current of virtual reality research has focused on building collab...
Benjamin Schaeffer, Mark Flider, Hank Kaczmarski, ...
CASES
2003
ACM
14 years 24 days ago
Frequent loop detection using efficient non-intrusive on-chip hardware
Dynamic software optimization methods are becoming increasingly popular for improving software performance and power. The first step in dynamic optimization consists of detecting ...
Ann Gordon-Ross, Frank Vahid