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ICML
1995
IEEE
14 years 1 months ago
Efficient Learning with Virtual Threshold Gates
Wolfgang Maass, Manfred K. Warmuth
DAC
2005
ACM
13 years 12 months ago
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
Feng Gao, John P. Hayes
CRYPTO
2008
Springer
80views Cryptology» more  CRYPTO 2008»
13 years 11 months ago
Dynamic Threshold Public-Key Encryption
Cécile Delerablée, David Pointcheval
AIA
2007
13 years 11 months ago
Minimizing leakage: What if every gate could have its individual threshold voltage?
Designers aim at fast but low-power consuming integrated circuits. Since high processing speed always comes with high energy demands, the literature provides several ways to reduc...
Ralf Salomon, Frank Sill, Dirk Timmermann