13 search results - page 1 / 3 » Tile Size Selection Using Cache Organization and Data Layout |
PLDI
1995
ACM
14 years 8 months ago
1995
ACM
When dense matrix computations are too large to fit in cache, previous research proposes tiling to reduce or eliminate capacity misses. This paper presents a new algorithm for ch...
PCI
2005
Springer
14 years 10 months ago
2005
Springer
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
IEEEPACT
2009
IEEE
14 years 11 months ago
2009
IEEE
—With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleave...
ICPP
2002
IEEE
14 years 10 months ago
2002
IEEE
Recently, several experimental studies have been conducted on block data layout as a data transformation technique used in conjunction with tiling to improve cache performance. In...
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VLDB
2002
ACM
15 years 5 months ago
2002
ACM
Relational database systems have traditionally optimized for I/O performance and organized records sequentially on disk pages using the N-ary Storage Model (NSM) (a.k.a., slotted ...