26 search results - page 3 / 6 » Tiling Imperfectly-Nested Loop Nests |
IJPP
1998
13 years 7 months ago
1998
This paper applies unimodular transformations and tiling to improve data locality of a loop nest. Due to data dependences and reuse information, not all dimensions of the iteration...
TJS
2002
13 years 7 months ago
2002
A significant source for enhancing application performance and for reducing power consumption in embedded processor applications is to improve the usage of the memory hierarchy. In...
SAC
2004
ACM
14 years 26 days ago
2004
ACM
This paper presents an overview of our work, concerning a complete end-to-end framework for automatically generating message passing parallel code for tiled nested for-loops. It c...
PPOPP
2011
ACM
12 years 10 months ago
2011
ACM
Time skewing and loop tiling has been known for a long time to be a highly beneficial acceleration technique for nested loops especially on bandwidth hungry multi-core processors...
TJS
2002
13 years 7 months ago
2002
This paper describes a tiling technique that can be used by application programmers and optimizing compilers to obtain I/O-efficient versions of regular scientific loop nests. Due ...