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» Tilings as a programming exercise
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ISCA
2010
IEEE
236views Hardware» more  ISCA 2010»
14 years 2 months ago
Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors
Next generation tiled microarchitectures are going to be limited by off-chip misses and by on-chip network usage. Furthermore, these platforms will run an heterogeneous mix of ap...
Enric Herrero, José González, Ramon ...
PASTE
2010
ACM
14 years 2 months ago
Opportunities for concurrent dynamic analysis with explicit inter-core communication
Multicore is now the dominant processor trend, and the number of cores is rapidly increasing. The paradigm shift to multicore forces the redesign of the software stack, which incl...
Jungwoo Ha, Stephen P. Crago
BMCBI
2008
148views more  BMCBI 2008»
13 years 10 months ago
Automating dChip: toward reproducible sharing of microarray data analysis
Background: During the past decade, many software packages have been developed for analysis and visualization of various types of microarrays. We have developed and maintained the...
Cheng Li
BMCBI
2006
115views more  BMCBI 2006»
13 years 9 months ago
SimArray: a user-friendly and user-configurable microarray design tool
Background: Microarrays were first developed to assess gene expression but are now also used to map protein-binding sites and to assess allelic variation between individuals. Rega...
Richard P. Auburn, Roslin R. Russell, Bettina Fisc...
CORR
2004
Springer
177views Education» more  CORR 2004»
13 years 9 months ago
Typestate Checking and Regular Graph Constraints
We introduce regular graph constraints and explore their decidability properties. The motivation for regular graph constraints is 1) type checking of changing types of objects in ...
Viktor Kuncak, Martin C. Rinard