652 search results - page 11 / 131 » Time Management in The High Level Architecture |
PAAMS
2010
Springer
13 years 6 months ago
2010
Springer
This presents a study in which a high level abstract architecture was used to design open multi-agent systems and virtual organizations that offer services with temporal constraint...
ISCAPDCS
2004
13 years 10 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
WECWIS
2002
IEEE
14 years 1 months ago
2002
IEEE
The demand for real-time data services has been increasing recently. Many e-commerce applications and webbased information services are becoming very sophisticated in their data n...
MICRO
1995
IEEE
14 years 4 days ago
1995
IEEE
Accurate instruction fetch and branch prediction is increasingly important on today’s wide-issue architectures. Fetch prediction is the process of determining the next instructi...