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» Time Management in The High Level Architecture
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APCSAC
2005
IEEE
14 years 2 months ago
The Challenges of Massive On-Chip Concurrency
Moore’s law describes the growth in on-chip transistor density, which doubles every 18 to 24 months and looks set to continue for at least a decade and possibly longer. This grow...
Kostas Bousias, Chris R. Jesshope
AIMS
2008
Springer
14 years 3 months ago
An Architecture for Supporting Network Fault Recovery Management
Highly available and resilient networks play a decisive role in today’s networked world. As network faults are inevitable and networks are becoming constantly intricate, finding...
Feng Liu, Antonis M. Hadjiantonis, Ha Manh Tran, M...
ICCD
2000
IEEE
125views Hardware» more  ICCD 2000»
14 years 5 months ago
Architectural Support for Dynamic Memory Management
Recent advances in software engineering, such as graphical user intevaces and object-oriented programming, have caused applications to become more memory intensive. These applicat...
J. Morris Chang, Witawas Srisa-an, Chia-Tien Dan L...
DATE
2007
IEEE
114views Hardware» more  DATE 2007»
14 years 3 months ago
Mapping the physical layer of radio standards to multiprocessor architectures
We are concerned with the software implementation of baseband processing for the physical layer of radio standards (“Software Defined Radio - SDR”). Given the constraints for ...
Cyprian Grassmann, Mathias Richter, Mirko Sauerman...
COMCOM
2002
120views more  COMCOM 2002»
13 years 8 months ago
The Cyclone Server Architecture: streamlining delivery of popular content
Abstract-We propose a new webserver architecture optimized for delivery of large, popular files. Delivery of such files currently pose a scalability problem for conventional conten...
Stanislav Rost, John W. Byers, Azer Bestavros