652 search results - page 72 / 131 » Time Management in The High Level Architecture |
MICRO
2007
IEEE
14 years 3 months ago
2007
IEEE
The microarchitectural design space of a new processor is too large for an architect to evaluate in its entirety. Even with the use of statistical simulation, evaluation of a sing...
RTAS
2010
IEEE
13 years 7 months ago
2010
IEEE
—Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which im...
VLDB
1999
ACM
14 years 1 months ago
1999
ACM
Recent high-performance processors employ sophisticated techniques to overlap and simultaneously execute multiple computation and memory operations. Intuitively, these techniques ...
AAI
2006
13 years 8 months ago
2006
The problem of finding a high quality timetable for personnel in a hospital ward has been addressed by many researchers, personnel managers and schedulers over a number of years. ...
EUROSSC
2009
Springer
14 years 3 months ago
2009
Springer
Several navigation situations can be imagined where visual cueing is not practical or unfeasible, and where the hands are required exclusively for a certain task. The utilization o...