Sciweavers

652 search results - page 87 / 131
» Time Management in The High Level Architecture
Sort
View
IPPS
2006
IEEE
14 years 2 months ago
An automated development framework for a RISC processor with reconfigurable instruction set extensions
By coupling a reconfigurable hardware to a standard processor, high levels of flexibility and adaptability are achieved. However, this approach requires modifications to the compi...
Nikolaos Vassiliadis, George Theodoridis, Spiridon...
DSRT
1999
IEEE
14 years 1 months ago
Collaborative Virtual Environment Standards: A Performance Evaluation
Collaborative Virtual Environments are virtual reality spaces that enable participants to collaborate and share objects as if physically present in the same place. These collabora...
Jauvane C. de Oliveira, Shervin Shirmohammadi, Nic...
DSRT
1999
IEEE
14 years 1 months ago
Agent-Aided Collaborative Virtual Environments Over HLA/RTI
This paper introduces a Collaborative Virtual Environment (CVE) system over the Internet. A Virtual Reality Modeling Language (VRML) 97-based user interface is developed to permit...
Xiaojun Shen, Ramsey Hage, Nicolas D. Georganas
ICPPW
1999
IEEE
14 years 1 months ago
Multistage Ring Network: A New Multiple Ring Network for Large Scale Multiprocessors
We present a new multiple ring network for multiprocessors, called the Multistage Ring Network(MRN). The MRN has a 2-level hierarchy of register insertion rings, and its interconn...
Dongho Yoo, Inbum Jung, Seung Ryoul Maeng, Hyungla...
VLSID
2000
IEEE
135views VLSI» more  VLSID 2000»
14 years 10 days ago
Performance and Functional Verification of Microprocessors
We address the problem of verifying the correctness of pre-silicon models of a microprocessor. We touch on the latest advances in this area by considering two different aspects of...
Pradip Bose, Jacob A. Abraham