Sciweavers

145 search results - page 17 / 29
» Time and memory tradeoffs in the implementation of AUTOSAR c...
Sort
View
VLSISP
2008
100views more  VLSISP 2008»
13 years 7 months ago
Memory-constrained Block Processing for DSP Software Optimization
Digital signal processing (DSP) applications involve processing long streams of input data. It is important to take into account this form of processing when implementing embedded ...
Ming-Yung Ko, Chung-Ching Shen, Shuvra S. Bhattach...
DATE
2006
IEEE
202views Hardware» more  DATE 2006»
14 years 1 months ago
Automatic systemC design configuration for a faster evaluation of different partitioning alternatives
In this paper we present a methodology that is based on SystemC [1] for rapid prototyping to greatly enhance and accelerate the exploration of complex systems to optimize the syst...
Nico Bannow, Karsten Haug, Wolfgang Rosenstiel
ISCA
2012
IEEE
260views Hardware» more  ISCA 2012»
11 years 9 months ago
A case for exploiting subarray-level parallelism (SALP) in DRAM
Modern DRAMs have multiple banks to serve multiple memory requests in parallel. However, when two requests go to the same bank, they have to be served serially, exacerbating the h...
Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Li...
CAD
2000
Springer
13 years 7 months ago
Time-critical multiresolution rendering of large complex models
Very large and geometrically complex scenes, exceeding millions of polygons and hundreds of objects, arise naturally in many areas of interactive computer graphics. Time-critical ...
Enrico Gobbetti, Eric Bouvier
IPPS
1994
IEEE
13 years 11 months ago
Parallel Evaluation of a Parallel Architecture by Means of Calibrated Emulation
A parallel transputer-based emulator has been developed to evaluate the DDM--ahighlyparallel virtual shared memory architecture. The emulator provides performance results of a har...
Henk L. Muller, Paul W. A. Stallard, David H. D. W...