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DAC
1999
ACM
13 years 11 months ago
Parallel Mixed-Level Power Simulation Based on Spatio-Temporal Circuit Partitioning
: In this work we propose a technique for spatial and temporal partitioning of a logic circuit based on the nodes activity computed by using a simulation at an higher level of ion....
Mauro Chinosi, Roberto Zafalon, Carlo Guardiani
IPPS
1996
IEEE
13 years 11 months ago
Parallel Algorithms for Image Enhancement and Segmentation by Region Growing with an Experimental Study
This paper presents e cient and portable implementations of a useful image enhancement process, the Symmetric Neighborhood Filter SNF, and an image segmentation technique which ma...
David A. Bader, Joseph JáJá, David H...
ASAP
2004
IEEE
101views Hardware» more  ASAP 2004»
13 years 11 months ago
Register Organization for Enhanced On-Chip Parallelism
Large register file with multiple ports is a critical component of a high-performance processor. A large number of registers are necessary for processing a larger number of in-fli...
Rama Sangireddy
ICCCN
2007
IEEE
14 years 1 months ago
Signaling Transport Options in GMPLS Networks: In-band or Out-of-band
—Signaling protocols for GMPLS networks have been standardized and implemented in switch controllers. Most switch vendors allow for signaling messages to be carried over inband s...
Malathi Veeraraghavan, Tao Li
NOSSDAV
2005
Springer
14 years 27 days ago
Power-efficient streaming for mobile terminals
Wireless Network Interface (WNI) is one of the most critical components for power efficiency in multimedia streaming to mobile devices. A common strategy to save power is to switc...
Jari Korhonen, Ye Wang