70 search results - page 4 / 14 » Time-Energy Design Space Exploration for Multi-Layer Memory ... |
142
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DATE
2008
IEEE
15 years 11 months ago
2008
IEEE
In this paper, we present an architecture exploration methodology for low-end embedded systems where the reduction of cost is a primary design concern. The architecture exploratio...
144
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ISCA
1994
IEEE
15 years 9 months ago
1994
IEEE
In the near future, semiconductor technology will allow the integration of multiple processors on a chip or multichipmodule (MCM). In this paper we investigate the architecture an...
163
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JSA
2007
15 years 5 months ago
2007
Multiprocessor system-on-chip (MP-SoC) platforms represent an emerging trend for embedded multimedia applications. To enable MP-SoC platforms, scalable communication-centric inter...
167
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SBACPAD
2008
IEEE
15 years 11 months ago
2008
IEEE
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
145
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ASPDAC
2008
ACM
15 years 7 months ago
2008
ACM
Horizontally Partitioned Caches (HPCs) are a promising architectural feature to reduce the energy consumption of the memory subsystem. However, the energy reduction obtained using...