411 search results - page 77 / 83 » Timed Alternating-Time Temporal Logic |
GLVLSI
2009
IEEE
14 years 4 months ago
2009
IEEE
In the context of formal verification Bounded Model Checking (BMC) has shown to be very powerful for large industrial designs. BMC is used to check whether a circuit satisfies a...
CEC
2008
IEEE
14 years 4 months ago
2008
IEEE
Abstract— Model Checking is a well-known and fully automatic technique for checking software properties, usually given as temporal logic formulae on the program variables. Most o...
CSFW
2005
IEEE
14 years 3 months ago
2005
IEEE
Modelling security policies requires means to specify permissions and prohibitions. However, this is generally not sufficient to express security properties such as availability ...
WONS
2005
IEEE
14 years 3 months ago
2005
IEEE
Due to the mobility of nodes in Ad hoc networks, network topology is dynamic and unpredictable, which leads to frequent network partitioning. This partitioning disconnects many no...
EUROCAST
2003
Springer
14 years 3 months ago
2003
Springer
This paper explores the computational capacity of a novel local computational model that expands the conventional analogical and logical dynamic neural models, based on the charge ...