769 search results - page 145 / 154 » Timed Circuit Synthesis Using Implicit Methods |
CDC
2009
IEEE
13 years 11 months ago
2009
IEEE
The central task of current profile control during the ramp-up phase of a tokamak discharge is to find the actuator trajectories that are necessary to achieve certain desired curre...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
Parallel processing using multiple processors is a well-established technique to accelerate many different classes of applications. However, as the density of chips increases, ano...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...
ASYNC
2003
IEEE
14 years 28 days ago
2003
IEEE
High-speed asynchronous ripple FIFOs may be easily embedded in synchronous environments and can elegantly handle the problem of forwarding data between clock domains. In cases whe...
SLIP
2003
ACM
14 years 26 days ago
2003
ACM
Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on adjacent wires on long bus lines can increase delay...