769 search results - page 38 / 154 » Timed Circuit Synthesis Using Implicit Methods |
FPL
2006
Springer
14 years 2 months ago
2006
Springer
FPGA devices exhibit manufacturing variability. Device ratings and Timing margins are typically used in order to cope with inter-device and intra-device variability respectively. ...
INTEGRATION
2008
13 years 10 months ago
2008
Physical synthesis is a relatively young field in Electronic Design Automation. Many published optimizations for physical synthesis end up hurting the quality of the final design,...
TCAD
2008
13 years 10 months ago
2008
BDDs have proven to be an efficient means to represent and manipulate Boolean formulae [1] and sets [2] due to their compactness and canonicality. In this work, we leverage the eff...
DATE
2007
IEEE
14 years 4 months ago
2007
IEEE
— We present a waveform based variational static timing analysis methodology. It is a timing paradigm that lies midway between convention static delay approximations and full dyn...
ASPDAC
2005
ACM
14 years 9 days ago
2005
ACM
- To date, most high-level synthesis systems do not automatically solve present design problems, such as those related to timing associated with the physical implementation of mult...