769 search results - page 92 / 154 » Timed Circuit Synthesis Using Implicit Methods |
ASPDAC
2008
ACM
14 years 2 days ago
2008
ACM
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
IOLTS
2009
IEEE
14 years 4 months ago
2009
IEEE
—Robust circuit design has become a major concern for nanoscale technologies. As a consequence, for design validation, not only the functionality of a circuit has to be considere...
FPGA
2004
ACM
14 years 3 months ago
2004
ACM
Traditional metrics used to compare hardware designs include area, performance, and power. However, these metrics do not form a complete evaluation of reconfigurable hardware. For...
GLVLSI
2003
IEEE
14 years 3 months ago
2003
IEEE
One of the fundamental problems in Deep Sub Micron (DSM) circuits is Simultaneous Switching Noise (SSN), which causes voltage fluctuations in the circuit power/ground networks. In...
DAC
2008
ACM
14 years 11 months ago
2008
ACM
Many recent techniques for timing analysis under variability, in which delay is an explicit function of underlying parameters, may be described as parameterized timing analysis. T...