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QSIC
2003
IEEE
14 years 4 months ago
Generating Small Combinatorial Test Suites to Cover Input-Output Relationships
In this paper, we consider a problem that arises in black box testing: generating small test suites (i.e., sets of test cases) where the combinations that have to be covered are s...
Christine Cheng, Adrian Dumitrescu, Patrick J. Sch...
RSP
2003
IEEE
117views Control Systems» more  RSP 2003»
14 years 4 months ago
Prototype-Based Tests for Hybrid Reactive Systems
Model-based testing relies on the use of behavior models to automatically generate sequences of inputs and expected outputs. These sequences can be used as test cases to the end o...
Gabor Hahn, Jan Philipps, Alexander Pretschner, Th...
DAC
2007
ACM
14 years 11 months ago
Scan Test Planning for Power Reduction
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...
CP
2009
Springer
14 years 11 months ago
Constraint-Based Optimal Testing Using DNNF Graphs
The goal of testing is to distinguish between a number of hypotheses about a systemfor example, dierent diagnoses of faults by applying input patterns and verifying or falsifying t...
Anika Schumann, Martin Sachenbacher, Jinbo Huang
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
14 years 5 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...