176 search results - page 20 / 36 » Timed Verification of Asynchronous Circuits |
DAC
2003
ACM
14 years 28 days ago
2003
ACM
Reduction of an extracted netlist is an important pre-processing step for techniques such as model order reduction in the design and analysis of VLSI circuits. This paper describe...
TPPP
1994
13 years 11 months ago
1994
We introduce a method for the specification of reactive asynchronous components with a concurrent access interface and outline its mathematical foundation. The method supports the...
FM
2003
Springer
14 years 26 days ago
2003
Springer
We present the formal framework for a novel approach for specifying and automatically implementing systems such as digital circuits and network protocols. The goal is to reduce the...
DAC
1990
ACM
13 years 11 months ago
1990
ACM
Symbolic simulation involves evaluating circuit behavior using special symbolic values to encode a range of circuit operating conditions. In one simulation run, a symbolic simulat...
EUSFLAT
2003
13 years 9 months ago
2003
Industrial processes can be often modelled using Petri nets. If all the process variables (or events) are assumed to be twovalued signals, then it is possible to obtain a hardware...