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WCET
2008
13 years 10 months ago
INFER: Interactive Timing Profiles based on Bayesian Networks
We propose an approach for timing analysis of software-based embedded computer systems that builds on the established probabilistic framework of Bayesian networks. We envision an ...
Michael Zolda
ISCA
2003
IEEE
93views Hardware» more  ISCA 2003»
14 years 2 months ago
Improving Dynamic Cluster Assignment for Clustered Trace Cache Processors
This work examines dynamic cluster assignment for a clustered trace cache processor (CTCP). Previously proposed cluster assignment techniques run into unique problems as issue wid...
Ravi Bhargava, Lizy Kurian John
DAC
2005
ACM
13 years 10 months ago
Smart diagnostics for configurable processor verification
This paper describes a novel technique called Embedded Test-bench Control (ETC), extensively used in the verification of Tensilica’s latest configurable processor. Conventional ...
Sadik Ezer, Scott Johnson
CASES
2005
ACM
13 years 10 months ago
Architectural support for real-time task scheduling in SMT processors
In Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architec...
Francisco J. Cazorla, Peter M. W. Knijnenburg, Riz...
RTCSA
2003
IEEE
14 years 2 months ago
Deterministic and Statistical Deadline Guarantees for a Mixed Set of Periodic and Aperiodic Tasks
Current hard real-time technologies are unable to support a new class of applications that have real-time constraints but with dynamic request arrivals and unpredictable resource r...
Minsoo Ryu, Seongsoo Hong