483 search results - page 29 / 97 » Timing Games and Shared Memory |
RTSS
2003
IEEE
14 years 3 months ago
2003
IEEE
Any data exchanged between the processor and main memory uses the memory bus, sharing it with data exchanged between I/O devices and main memory. If the processor and a device try...
IPPS
2006
IEEE
14 years 3 months ago
2006
IEEE
Granularity control is an effective means for trading power consumption with performance on dense shared memory multiprocessors, such as multi-SMT and multi-CMP systems. In this p...
IPPS
2007
IEEE
14 years 4 months ago
2007
IEEE
This paper explores generating efficient, portable HighSpeed Producer Consumer (HSPC) code on current shared memory architectures: Chip Multi-Processors (CMP), Simultaneous Multi...
IEEEPACT
1998
IEEE
14 years 2 months ago
1998
IEEE
In order to achieve practical efficient execution on a parallel architecture, a knowledge of the data dependencies related to the application appears as the key point for building...
ISCA
1994
IEEE
14 years 2 months ago
1994
IEEE
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...