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IPPS
1999
IEEE
14 years 2 months ago
A Graph Based Framework to Detect Optimal Memory Layouts for Improving Data Locality
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
ICCAD
2009
IEEE
179views Hardware» more  ICCAD 2009»
13 years 7 months ago
Automatic memory partitioning and scheduling for throughput and power optimization
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
Jason Cong, Wei Jiang, Bin Liu, Yi Zou
ISCA
2012
IEEE
279views Hardware» more  ISCA 2012»
12 years 10 days ago
Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
Rachata Ausavarungnirun, Kevin Kai-Wei Chang, Lava...
CCECE
2006
IEEE
14 years 4 months ago
Lazy Generation of Building Interiors in Realtime
Impenetrable doors are often quite common in virtual worlds. This is especially apparent in video games boasting large urban environments. Although there are often enterable build...
Evan Hahn, Prosenjit Bose, Anthony Whitehead
COLCOM
2007
IEEE
14 years 4 months ago
Multicasting in groupware?
— While multicast has been studied extensively in many domains such as content streaming and file sharing, there is little research applying it to synchronous collaborations invo...
Sasa Junuzovic, Prasun Dewan