483 search results - page 5 / 97 » Timing Games and Shared Memory |
PPOPP
2009
ACM
14 years 10 months ago
2009
ACM
Transactional Memory (TM) is being studied widely as a new technique for synchronizing concurrent accesses to shared memory data structures for use in multi-core systems. Much of ...
HPCA
2004
IEEE
14 years 10 months ago
2004
IEEE
Much research has been devoted to making microprocessors energy-efficient. However, little attention has been paid to multiprocessor environments where, due to the co-operative na...
ISCA
1997
IEEE
14 years 2 months ago
1997
IEEE
Current microprocessors aggressively exploit instructionlevel parallelism (ILP) through techniques such as multiple issue, dynamic scheduling, and non-blocking reads. Recent work ...
HICSS
1995
IEEE
14 years 1 months ago
1995
IEEE
The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable in...
TWC
2010
13 years 4 months ago
2010
We propose a wireless access scheme which is based on a channel reservation sharing method for a group of mobile users. This proposed scheme exploits the mobility diversity of the ...