4164 search results - page 22 / 833 » Timing model reduction for hierarchical timing analysis |
QEST
2007
IEEE
14 years 3 months ago
2007
IEEE
Among the many stages of a simulation study, debugging a simulation model is the one that is hardly reported on but that may consume a considerable amount of time and effort. In t...
ICPR
2004
IEEE
14 years 10 months ago
2004
IEEE
Boosting-basedmethods have recently led to the state-ofthe-art face detection systems. In these systems, weak classifiers to be boosted are based on simple, local, Haar-like featu...
SODA
2012
ACM
11 years 11 months ago
2012
ACM
We study the role that parallelism plays in time complexariants of Winfree’s abstract Tile Assembly Model (aTAM), a model of molecular algorithmic self-assembly. In the “hiera...
DDECS
2007
IEEE
14 years 3 months ago
2007
IEEE
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
ISCAS
2003
IEEE
14 years 2 months ago
2003
IEEE
We propose an algorithm based on singular value decomposition (SVD) to reduce the number of process variation variables. With few process variation variables, fault simulation and...