An effort to formalize the process of software pipelining loops with conditions is presented in this paper. A formal framework for scheduling such loops, based on representing set...
High-level synthesis (HLS) requires more designer interaction to better meet the needs of experienced designers. However, attempts to create a highly interactive synthesis process...
In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity...
Abstract. We present a formal framework for syntax directed probabilistic program analysis. Our focus is on probabilistic pointer analysis. We show how to obtain probabilistic poin...
Alessandra Di Pierro, Chris Hankin, Herbert Wiklic...
We present a transport protocol whose goal is to reduce power consumption without compromising delivery requirements of applications. To meet its goal of energy efficiency, our tr...
Niky Riga, Ibrahim Matta, Alberto Medina, Craig Pa...