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» Tolerance Models in Hardware Description Languages
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ASAP
2008
IEEE
105views Hardware» more  ASAP 2008»
13 years 10 months ago
Fast custom instruction identification by convex subgraph enumeration
Automatic generation of custom instruction processors from high-level application descriptions enables fast design space exploration, while offering very favorable performance and...
Kubilay Atasu, Oskar Mencer, Wayne Luk, Can C. &Ou...
ANSS
2005
IEEE
14 years 2 months ago
The Bubble Bit Technique as Improvement of HDL-Based Quantum Circuits Simulation
When performed on a classical computer, the simulation of quantum circuits is usually an exponential job. The methodology based on Hardware Description Languages is able to isolat...
Mihai Udrescu, Lucian Prodan, Mircea Vladutiu
FDL
2005
IEEE
14 years 2 months ago
Incorporating SystemC in Analog/Mixed-Signal Design Flow
In today’s flows, there is still a gap between system level description and hardware implementation, especially for analog/RF building blocks. SystemC-AMS or co-simulations have...
Patrick Birrer, Walter Hartong
ASPLOS
2010
ACM
14 years 3 months ago
Specifying and dynamically verifying address translation-aware memory consistency
Computer systems with virtual memory are susceptible to design bugs and runtime faults in their address translation (AT) systems. Detecting bugs and faults requires a clear speciï...
Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. So...
ECBS
2005
IEEE
160views Hardware» more  ECBS 2005»
14 years 2 months ago
Traceability-Driven Model Refinement for Test Case Generation
Testing complex Computer-Based Systems is not only a demanding but a very critical task. Therefore the use of models for generating test data is an important goal. Tool support du...
Matthias Riebisch, Michael Hübner