43 search results - page 7 / 9 » Tolerant Locally Testable Codes |
PPL
2006
13 years 8 months ago
2006
This paper analyses the micro-threaded model of concurrency making comparisons with both data and instruction-level concurrency. The model is fine grain and provides synchronisati...
ISCA
1999
IEEE
14 years 25 days ago
1999
IEEE
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
TCC
2005
Springer
14 years 2 months ago
2005
Springer
We initiate a study of Maurer’s bounded storage model (JoC, 1992) in presence of transmission errors and perhaps other types of errors that cause different parties to have incon...
PDP
2011
IEEE
13 years 7 days ago
2011
IEEE
Abstract—Continuously reducing transistor sizes and aggressive low power operating modes employed by modern architectures tend to increase transient error rates. Concurrently, mu...
ISLPED
2005
ACM
14 years 2 months ago
2005
ACM
ABSTRACT Motivated by data value locality and quality tolerance present in multimedia applications, we propose a new micro-architecture, Region-level Approximate Computation Buffer...