48 search results - page 3 / 10 » Tolerating data access latency with register preloading |
HPCC
2009
Springer
13 years 11 months ago
2009
Springer
Usual cache optimisation techniques for high performance computing are difficult to apply in embedded VLIW applications. First, embedded applications are not always well structur...
SIAMCOMP
2010
13 years 1 months ago
2010
We study efficient and robust implementations of an atomic read-write data structure over an asynchronous distributed message-passing system made of reader and writer processes, as...
MICRO
1995
IEEE
13 years 10 months ago
1995
IEEE
Untolerated load instruction latencies often have a significant impact on overall program performance. As one means of mitigating this effect, we present an aggressive hardware-b...
PPL
2006
13 years 7 months ago
2006
This paper analyses the micro-threaded model of concurrency making comparisons with both data and instruction-level concurrency. The model is fine grain and provides synchronisati...
ICPP
1994
IEEE
13 years 11 months ago
1994
IEEE
Both hardware and software prefetching have been shown to be e ective in tolerating the large memory latencies inherent in shared-memory multiprocessors however, both types of pre...