39 search results - page 5 / 8 » Tolerating node failures in cache only memory architectures |
CASES
2003
ACM
14 years 3 months ago
2003
ACM
Recent research in sensor networks has raised issues of security for small embedded devices. Security concerns are motivated by the deployment of a large number of sensory devices...
SRDS
2007
IEEE
14 years 4 months ago
2007
IEEE
Fault tolerant distributed protocols typically utilize a homogeneous fault model, either fail-crash or fail-Byzantine, where all processors are assumed to fail in the same manner....
ACSAC
2008
IEEE
14 years 4 months ago
2008
IEEE
Main memory contains transient information for all resident applications. However, if memory chip contents survives power-off, e.g., via freezing DRAM chips, sensitive data such a...
ASWSD
2004
Springer
14 years 3 months ago
2004
Springer
– A safety-critical real-time computer system must provide its services with a dependability that is much better than the dependability of any one of its constituent components. ...
IPPS
1999
IEEE
14 years 2 months ago
1999
IEEE
In this paper we propose a simple extension to the I/O architecture of scalable multiprocessors that optimizes page swap-outs significantly. More specifically, we propose the use o...