39 search results - page 6 / 8 » Tolerating node failures in cache only memory architectures |
HPCA
1997
IEEE
14 years 3 months ago
1997
IEEE
Many parallel systems offer a simple view of memory: all storage cells are addresseduniformly. Despite a uniform view of the memory, the machines differsignificantly in theirmemo...
JPDC
2010
13 years 9 months ago
2010
Non-uniform memory architectures with cache coherence (ccNUMA) are becoming increasingly common, not just for large-scale high performance platforms but also in the context of mul...
FTCS
1997
14 years 5 days ago
1997
This paper presents robust emulation of multi-writer/multi-reader registers in message-passing systems using dynamic quorum con gurations. In addition to processor and link failur...
HPCA
2009
IEEE
14 years 11 months ago
2009
IEEE
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
GLOBECOM
2006
IEEE
14 years 4 months ago
2006
IEEE
The seamless and flexible interconnection of the existing and emerging protocols and networks is essential to the success of the new generation mobile applications and services. Fo...