In this paper, we formulate the problem of topology constrained rectilinear block packing in layout reuse. A speci c class of rectilinear shaped blocks, ordered convex rectilinear...
— In order to achieve timing closure on increasingly complex IC designs, buffer insertion needs to be performed on thousands of nets within an integrated physical synthesis syste...
Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jia...