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» Total leakage power optimization with improved mixed gates
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ISVLSI
2007
IEEE
184views VLSI» more  ISVLSI 2007»
14 years 1 months ago
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
GLVLSI
2000
IEEE
145views VLSI» more  GLVLSI 2000»
13 years 12 months ago
CMOS system-on-a-chip voltage scaling beyond 50nm
† The limits on CMOS energy dissipation imposed by subthreshold leakage currents and by wiring capacitance are investigated for CMOS generations beyond 50nm at NTRS projected loc...
Azeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoo...
ASPDAC
2007
ACM
121views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks
Power supply noise increases the circuit delay, which may lead to performance failure of a design. Decoupling capacitance (decap) addition is effective in reducing the power suppl...
Sanjay Pant, David Blaauw
TCSV
2008
128views more  TCSV 2008»
13 years 7 months ago
Compression-Aware Energy Optimization for Video Decoding Systems With Passive Power
The objective of dynamic voltage scaling (DVS) is to adapt the frequency and voltage for configurable platforms to obtain energy savings. DVS is especially attractive for video dec...
Emrah Akyol, Mihaela van der Schaar
PATMOS
2007
Springer
14 years 1 months ago
Optimization for Real-Time Systems with Non-convex Power Versus Speed Models
Abstract. Until now, the great majority of research in low-power systems has assumed a convex power model. However, recently, due to the confluence of emerging technological and ar...
Ani Nahapetian, Foad Dabiri, Miodrag Potkonjak, Ma...