48 search results - page 5 / 10 » Toward Formalizing a Validation Methodology Using Simulation... |
JSS
2008
13 years 8 months ago
2008
The increasing trend toward complex software systems has highlighted the need to incorporate quality requirements earlier in the development cycle. We propose a new methodology fo...
DATE
2008
IEEE
14 years 3 months ago
2008
IEEE
Despite the growing research effort in formal verification, constraint-based random simulation remains an integral part of design validation, especially for large design componen...
UML
2004
Springer
14 years 1 months ago
2004
Springer
Abstract. In this paper, we propose a verification methodology for System-OnChip (SoC) design using Unified Modeling Language (UML). We introduce UML as a formal model to analyze a...
ICDCS
2010
IEEE
13 years 10 months ago
2010
IEEE
Abstract—Coverage problem is a fundamental issue in wireless ad hoc and sensor networks. Previous techniques for coverage scheduling often require accurate location information o...
FMICS
2009
Springer
14 years 3 months ago
2009
Springer
on Abstraction: a Lightweight Approach to Modelling Concurrency. Javier de Dios and Ricardo Peña Certified Implementation on top of the Java Virtual Machine 19:00 Social dinner + ...