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» Towards Integrated Verification of Timed Transition Models
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ACSD
2006
IEEE
109views Hardware» more  ACSD 2006»
13 years 9 months ago
Synthesis of Synchronous Interfaces
Reuse of IP blocks has been advocated as a means to conquer the complexity of today's system-on-chip (SoC) designs. Component integration and verification in such systems is ...
Purandar Bhaduri, S. Ramesh
ATAL
2006
Springer
13 years 11 months ago
Verifying space and time requirements for resource-bounded agents
The effective reasoning capability of an agent can be defined as its capability to infer, within a given space and time bound, facts that are logical consequences of its knowledge...
Natasha Alechina, Mark Jago, Piergiorgio Bertoli, ...
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
14 years 7 days ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
TCAD
2002
146views more  TCAD 2002»
13 years 7 months ago
Static scheduling of multidomain circuits for fast functional verification
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
Murali Kudlugi, Russell Tessier
AICT
2006
IEEE
210views Communications» more  AICT 2006»
14 years 1 months ago
Model-Based Analysis of Obligations in Web Service Choreography
In this paper we discuss a model-based approach to the analysis of service interactions for coordinated web service compositions using obligation policies specified in the form of...
Howard Foster, Sebastián Uchitel, Jeff Mage...