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» Towards Nanoelectronics Processor Architectures
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ISSS
1999
IEEE
131views Hardware» more  ISSS 1999»
13 years 12 months ago
Compressed Code Execution on DSP Architectures
Decreasing the program size has become an important goal in the design of embedded systems target to mass production. This problem has led to a number of efforts aimed at designin...
Paulo Centoducatte, Ricardo Pannain, Guido Araujo
ISPAN
1997
IEEE
13 years 11 months ago
CASS: an efficient task management system for distributed memory architectures
The thesis of this research is that the task of exposing the parallelism in a given application should be left to the algorithm designer, who has intimate knowledge of the applica...
Jing-Chiou Liou, Michael A. Palis
ASPLOS
1992
ACM
13 years 11 months ago
Efficient Superscalar Performance Through Boosting
The foremost goal of superscalar processor design is to increase performance through the exploitation of instruction-level parallelism (ILP). Previous studies have shown that spec...
Michael D. Smith, Mark Horowitz, Monica S. Lam
CF
2008
ACM
13 years 9 months ago
A modular 3d processor for flexible product design and technology migration
The current methodology used in mass-market processor design is to create a single base microarchitecture (e.g., Intel's "Core"or AMD's"K8") that is ...
Gabriel H. Loh
VLDB
1999
ACM
145views Database» more  VLDB 1999»
13 years 11 months ago
DBMSs on a Modern Processor: Where Does Time Go?
Recent high-performance processors employ sophisticated techniques to overlap and simultaneously execute multiple computation and memory operations. Intuitively, these techniques ...
Anastassia Ailamaki, David J. DeWitt, Mark D. Hill...