Sciweavers

133 search results - page 19 / 27
» Towards Nanoelectronics Processor Architectures
Sort
View
ICPP
2006
IEEE
14 years 1 months ago
A Coarse Grained Parallel Algorithm for Hausdorff Voronoi Diagrams
We present the first parallel algorithm for building a Hausdorff Voronoi diagram (HVD). Our algorithm is targeted towards cluster computing architectures and computes the Hausdor...
Frank K. H. A. Dehne, Anil Maheshwari, Ryan Taylor
ECRTS
2007
IEEE
14 years 1 months ago
Cache-Aware Timing Analysis of Streaming Applications
Of late, there has been a considerable interest in models, algorithms and methodologies specifically targeted towards designing hardware and software for streaming applications. ...
Samarjit Chakraborty, Tulika Mitra, Abhik Roychoud...
MICRO
2006
IEEE
155views Hardware» more  MICRO 2006»
14 years 1 months ago
In-Network Cache Coherence
With the trend towards increasing number of processor cores in future chip architectures, scalable directory-based protocols for maintaining cache coherence will be needed. Howeve...
Noel Eisley, Li-Shiuan Peh, Li Shang
CSUR
2004
144views more  CSUR 2004»
13 years 7 months ago
Advances in dataflow programming languages
Many developments have taken place within dataflow programming languages in the past decade. In particular, there has been a great deal of activity and advancement in the field of ...
Wesley M. Johnston, J. R. Paul Hanna, Richard J. M...
SIGADA
2001
Springer
13 years 12 months ago
Targeting Ada95/DSA for distributed simulation of multiprotocol communication networks
The last years have seen an increasing, albeit restricted simulation of large-scale networks on shared memory parallel platforms. As the complexity of communication protocols and ...
Dhavy Gantsou