91 search results - page 15 / 19 » Towards a Thread-Based Parallel Direct Execution Simulator |
HPCA
2001
IEEE
14 years 8 months ago
2001
IEEE
Mispredicted branches and loads that miss in the cache cause the majority of retirement stalls experienced by sequential processors; we call these critical instructions. Despite t...
ICPP
1994
IEEE
14 years 17 days ago
1994
IEEE
Shared memory in a parallel computer provides prowith the valuable abstraction of a shared address space--through which any part of a computation can access any datum. Although un...
ECRTS
2007
IEEE
14 years 2 months ago
2007
IEEE
Uniprocessor schedulability theory made great strides, in part, due to the simplicity of composing the delay of a job from the execution times of higher-priority jobs that preempt...
IPPS
2002
IEEE
14 years 1 months ago
2002
IEEE
Tiling has long been used to improve cache performance. Recursion has recently been used as a cache-oblivious method of improving cache performance. Both of these techniques are n...
IPPS
2000
IEEE
14 years 25 days ago
2000
IEEE
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...