The ultimate goal of logic synthesis is to explore implementation flexibility toward meeting design targets, such as area, power, and delay. Traditionally, such flexibility is exp...
— We consider the design of a sensor network for detecting an emitter who if present is known to be located in an interval but whose exact position is unknown. We seek to minimiz...
In this paper we characterize the latency of the BSD 4.4 alpha implementation of TCP on an ATM network. Latency reduction is a difficult task, and careful analysis is the first st...
Alec Wolman, Geoffrey M. Voelker, Chandramohan A. ...
Supporting students in the acquisition of argumentation skills is an important goal of educational technology. However, there has not been much work done towards developing generi...
Frank Loll, Niels Pinkwart, Oliver Scheuer, Bruce ...
Formal, modular, and mechanized verification of realistic systems code is desirable but challenging. Verification of machine context management (a basis of multi-tasking) is one ...