190 search results - page 30 / 38 » Towards model checking interpreted systems |
SACMAT
2009
ACM
14 years 1 months ago
2009
ACM
The recent emergence of mandatory access (MAC) enforcement for virtual machine monitors (VMMs) presents an opportunity to enforce a security goal over all its virtual machines (VM...
SIGSOFT
2007
ACM
14 years 8 months ago
2007
ACM
Automated verification is a technique for establishing if certain properties, usually expressed in temporal logic, hold for a system model. The model can be defined using a high-l...
QEST
2009
IEEE
14 years 2 months ago
2009
IEEE
—Traviando is a trace analyzer and visualizer for simulation traces of discrete event dynamic systems. In this paper, we briefly outline recent extensions of Traviando towards a...
IWSSD
1993
IEEE
13 years 11 months ago
1993
IEEE
In this paper, we propose the use of fine-grain process modelling as an aid to software development. We suggest the use of two levels of granularity, one at the level of the indiv...
VMCAI
2004
Springer
14 years 22 days ago
2004
Springer
Typed Assembly Languages (TALs) can be used to validate the safety of assembly-language programs. However, typing rules are usually trusted as axioms. In this paper, we show how to...